Most of the GaN devices currently available on the market are lateral-type devices, which form a gallium nitride active layer on a silicon substrate. This allows for the high-frequency characteristics of GaN to be achieved at relatively low cost. However, it is usually difficult for silicon-based GaN devices to reach breakdown voltages of 650V or above.

In comparison to lateral-type devices, vertical GaN devices can simultaneously achieve higher voltage and greater current capabilities. Therefore, many companies are striving towards the development of vertical-type devices. However, the cost of developing vertical GaN devices is too high. As we all know, gallium nitride substrates are expensive and come in small sizes (2-4 inches).

On May 12th, the European YESvGaN Alliance showcased a new vertical GaN power transistor solution at PCIM Europe 2023. The cost of this solution can be reduced to be on par with silicon-based gallium nitride devices.

The YESvGaN Alliance is a European research project composed of 23 companies/organizations from seven countries, including STMicroelectronics, Soitec, and X-FAB. It was established with the support of the European Union's ECSEL JU research and development program and national funding from European countries. In 2021, the project officially launched with the aim of studying new vertical GaN power transistors.

According to the introduction, the alliance is developing a "vertical GaN thin-film transistor" technology that eliminates the use of gallium nitride substrates and instead utilizes silicon and sapphire substrates, achieving cost advantages through gallium nitride heteroepitaxial growth.

Simply put, after the growth of gallium nitride, they remove the underlying silicon, sapphire substrate, and buffer layer below the device area, and directly connect to the GaN layer's metal contacts from the backside.

The goal of this technology is to develop quasi-vertical GaN power transistors with breakdown voltages ranging from 650V to 1200V, using 12-inch (300mm) silicon or sapphire wafers. It aims to combine the advantages of vertical structures with the cost advantages of silicon-based GaN/sapphire GaN.

It is reported that they will take the following steps to achieve the aforementioned goals:

• Develop technology for growing thick drift layers on silicon and sapphire substrates using epitaxy, targeting 300mm wafer diameter to achieve breakdown voltage levels of 650-1200V.

• Develop vertically-oriented GaN power transistors with costs comparable to silicon IGBTs, reaching up to 1200V/100A with an on-resistance of 4mΩcm2.

• Utilize advanced bonding and peeling techniques to remove the silicon substrate and buffer layer through dry etching, enhance the sapphire substrate through laser lift-off and formation of ohmic contacts, and perform power metallization on the backside.

• Develop new packaging and interconnect technologies for the developed vertical GaN power transistors, and conduct corresponding reliability assessments.

• Create datasheets for the power transistors and showcase system efficiency improvements in several application demonstrations.

At this year's PCIM, YESvGaN showcased three process achievements:

1. Vertical GaN diodes grown on silicon/sapphire substrates with breakdown voltages exceeding 500V.

2. Silicon substrate peeling achieved on a 150mm silicon-based gallium nitride wafer.

3. Formation of defect-free gallium nitride thin films with a maximum diameter of 5mm and thickness of 4 micrometers.

They stated, "Although we have not yet reached the final stage of transistor production, we continue our research. Once this technology is realized, we expect to accelerate large-scale production of vertical gallium nitride."

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Gallium Nitride Wafer (GaN Wafer)