Introduction

Silicon carbide (SiC) substrates are among the most challenging single-crystal materials to manufacture in the semiconductor industry. Featuring complex growth procedures, long production cycles and strict defect control requirements, SiC substrates represent a core technical barrier in the global SiC industry. Currently, commercial SiC single-crystal substrates are mass-produced predominantly through the traditional Physical Vapor Transport (PVT) method. Meanwhile, the Smart‑Cut (SmartSiC™) engineered substrate technology developed by SOITEC breaks the material utilization bottlenecks of conventional single-crystal growth, providing a brand-new industry solution for cost reduction and efficiency improvement.
Based on original experimental data and process principles from authoritative academic papers, this article thoroughly analyzes the process flow, core advantages, technical challenges and industrialization status of the two mainstream SiC substrate manufacturing technologies, and systematically sorts out the iteration logic of SiC substrate technology.

1. Industrial Mainstream: PVT Single-Crystal Growth Technology

Physical Vapor Transport (PVT), also known as the modified Lely method, is currently the only technology globally capable of large-scale automotive-grade mass production of SiC substrates. More than 99% of commercial 4H‑SiC single-crystal boules and wafers on the market are manufactured via the PVT process.

1.1 Core Process Flow

Relying on high-temperature crucible equipment, the PVT process realizes the slow growth of SiC single crystals through precise control of temperature gradient, air pressure, atmosphere and other parameters. The entire procedure consists of three core stages:

• Sublimation Stage: Under high-temperature conditions, SiC powder raw materials inside the crucible sublimate and decompose into active gaseous silicon and carbon components.

• Mass Transport Stage: Guided by the preset internal temperature gradient, gaseous components migrate directionally from the high-temperature zone to the low-temperature seed crystal zone.

• Crystallization Growth Stage: Gaseous components react and recrystallize on the surface of low-temperature single-crystal seed crystals, gradually growing into complete SiC single-crystal boules.

After crystal growth is completed, the SiC boule undergoes multiple processes including cutting, grinding, polishing and cleaning to form bare substrate wafers. An epitaxial reactor is then used to grow surface epitaxial layers, producing epitaxial wafers ready for formal device manufacturing.
 

【Figure 1: Schematic Diagram of SiC Substrate and Epitaxial Layer Growth Structure】

1.2 Core Limitations of the PVT Process

After decades of technical iteration, the PVT process has achieved mature mass production. However, restricted by its physical growth mechanism, it has inherent shortcomings that hinder substrate cost reduction and capacity expansion:

• Extremely long growth cycle: A single SiC boule requires several days of non-stop growth, resulting in high equipment occupancy and slow capacity expansion.

• Low material utilization rate: Substantial material loss occurs during boule cutting and polishing, failing to fully utilize high-cost single-crystal materials.

• Difficult defect control: Large-size boule growth easily generates thermal stress, inducing native defects such as micropipes, dislocations and stacking faults. Larger wafer sizes bring greater challenges to defect management.

• Persistent high costs: Long production cycles, low material utilization and limited yield make it difficult to rapidly reduce the cost of high-quality SiC substrates.

2. Technological Innovation: SOITEC Smart‑Cut Engineered Substrate Technology

To break the inherent bottlenecks of the PVT process, SOITEC optimized the thin-layer transfer technology maturely applied to SOI silicon wafers and launched the SiC-adapted Smart‑Cut process. The innovative SmartSiC™ engineered composite substrate completely reconstructs the SiC substrate manufacturing logic and solves the long-standing industry pain point of low single-crystal material utilization.

2.1 Core Process Flow

Abandoning the traditional integral single-crystal growth mode, this technology adopts a composite structure of single-crystal thin-layer transfer + polycrystalline substrate support, with the specific process as follows:

• Substrate Preparation: High-quality PVT-grown single-crystal SiC is selected as the donor wafer (providing the device-level single-crystal surface layer), and ultra-high conductivity polycrystalline SiC is adopted as the supporting base wafer.

• Ion Implantation: Precise ion implantation is performed on the donor wafer to preset a thin-layer separation interface.

• Bonding: High-precision conductive bonding is realized between the donor wafer and the polycrystalline supporting wafer.

• Splitting and Transferring: Accurate splitting is carried out along the ion implantation layer, transferring the ultra-thin single-crystal SiC thin film onto the surface of the polycrystalline substrate.

• Polishing and Finishing: Precision polishing is applied to the surface layer to obtain SmartSiC™ engineered substrates that meet flatness and cleanliness standards.

• Wafer Reuse: The stripped donor wafer can be repaired and reused for multiple thin-layer transfer processes, with a reuse frequency of more than 10 times.
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【Figure 2: SOITEC Smart Cut SiC Wafer Manufacturing Process Flowchart】
 

2.2 Core Advantages of SmartSiC™ Substrates

• Greatly improved single-crystal utilization: Costly single-crystal donor wafers can be recycled multiple times, eliminating material waste in traditional PVT processes and significantly reducing raw material costs.

• Superior device performance: The high-conductivity polycrystalline base supports higher current density and smaller chip size design, increasing die output per wafer and boosting production density.

• Simplified process and lower cost: Composite substrates feature higher flatness and lower surface defect density, simplifying the subsequent backside ohmic contact manufacturing process without high-temperature annealing, reducing process steps and improving production yield.

• Adaptable to large-size iteration: This technology is highly compatible with 200mm large-size wafer manufacturing, serving as a key alternative technology for future large-scale mass production of high-size SiC substrates.

2.3 Existing Technical Shortcomings

Although the Smart‑Cut technology has entered initial industrialization, it still faces engineering challenges: tiny defects easily occur at the thin-layer transfer interface, the stability of the bonding interface requires long-term verification, and the yield of large-size wafer transfer needs further improvement. For now, it cannot completely replace traditional PVT single-crystal substrates. It is mainly applied in mid-to-high-end industrial scenarios, while large-scale automotive-grade application still requires continuous technical iteration.

3. Comprehensive Comparison of the Two Substrate Manufacturing Technologies

Comparison Dimension	PVT Native Single-Crystal Substrate	Smart‑Cut Engineered Substrate (SmartSiC™)
Core Principle	Integral single-crystal growth in high-temperature crucibles	Single-crystal thin-layer transfer + polycrystalline substrate composite bonding
Single-Crystal Utilization Rate	Low, massive cutting loss and non-reusable	Extremely high, donor wafers can be reused over 10 times
Substrate Material	Full single-crystal SiC	Composite structure of high-conductivity polycrystalline SiC + single-crystal thin layer
Process Maturity	Extremely high, fully mature for automotive-grade mass production	Medium, under industrialization and automotive qualification verification
Core Pain Points	Long growth cycle, slow capacity expansion, high cost, difficult defect control
Application Scenarios	Stringent scenarios such as automotive, aerospace and high-end industry	Cost-effective scenarios including general industry, photovoltaic and energy storage

Conclusion

At this stage, PVT native single-crystal substrates remain the absolute mainstream of the SiC industry and the only qualified choice for high-end automotive and aerospace devices. Benefiting from extreme material utilization and cost advantages, Smart‑Cut engineered substrate technology has become a core breakthrough for industrial cost reduction and capacity expansion. The two technologies will complement and iterate with each other in the long run, jointly promoting the upgrading of SiC substrates toward larger size, lower defect density and lower cost. Process defects derived from substrate doping, annealing, etching and oxidation will continue to restrict device performance, which will be deeply analyzed in the next article focusing on backend process challenges and the complete industrial technology roadmap.
JXT provides professional 2–12 inch full-specification silicon carbide substrates, covering small-size R&D samples to large-scale mass production demands. With low defect density and high flatness, our products adapt well to the R&D and mass production of both mainstream PVT processes and innovative composite substrate technologies.